The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Jun. 30, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Hajime Kimura, Yokkaichi, JP;

Seiji Shimabukuro, Yokkaichi, JP;

Shuji Minagawa, Yokkaichi, JP;

Michiaki Sano, Ichinomiya, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1157 (2013.01); H01L 27/11517 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively. The support pillar structures are formed with an outermost dielectric layer to prevent a leakage path to electrically conductive layers to be subsequently formed.


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