The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Mar. 25, 2016
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hsin-Ying Lin, Tainan, TW;
Mei-Yun Wang, Chu-Pei, TW;
Hsien-Cheng Wang, Hsinchu, TW;
Shih-Wen Liu, Taoyuan, TW;
Fu-Kai Yang, Hsinchu, TW;
Audrey Hsiao-Chiu Hsu, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.