The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 2017

Filed:

Apr. 24, 2015
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Keren Jacobs Kanarik, Los Altos, CA (US);

Jeffrey Marks, Saratoga, CA (US);

Harmeet Singh, Fremont, CA (US);

Samantha Tan, Fremont, CA (US);

Alexander Kabansky, Santa Clara, CA (US);

Wenbing Yang, Fremont, CA (US);

Taeseung Kim, San Jose, CA (US);

Dennis M. Hausmann, Lake Oswego, OR (US);

Thorsten Lill, Santa Clara, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 21/30655 (2013.01); H01L 21/0228 (2013.01); H01L 21/31116 (2013.01); H01L 21/67069 (2013.01); H01L 21/67207 (2013.01); H01L 21/6831 (2013.01);
Abstract

Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.


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