The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Dec. 09, 2015
Mediatek Inc., Hsin-Chu, TW;
Ming-Tzong Yang, Baoshan Township, Hsinchu County, TW;
Cheng-Chou Hung, Hukou Township, Hsinchu County, TW;
Wei-Che Huang, Zhudong Township, Hsinchu County, TW;
Yu-Hua Huang, Hsinchu, TW;
Tzu-Hung Lin, Zhubei, TW;
Kuei-Ti Chan, Hsinchu, TW;
Ruey-Beei Wu, Taipei, TW;
Kai-Bin Wu, Kaohsiung, TW;
MediaTek Inc., Hsin-Chu, TW;
Abstract
The invention provides a semiconductor package assembly with a TSV interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed through the semiconductor substrate, wherein the first array and second array of TSV interconnects are separated by an interval region. A first ground TSV interconnect is disposed within the interval region. A second semiconductor die is mounted on the first semiconductor die, having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to an interconnection structure disposed on a front side of the semiconductor substrate.