The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Sep. 09, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Ding Wang, Tainan, TW;

Jung Wei Cheng, Hsinchu, TW;

Bo-I Lee, Sindian, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 21/302 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3185 (2013.01); H01L 21/302 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3178 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 23/3114 (2013.01); H01L 23/3192 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 2221/6834 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/0558 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05611 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/05666 (2013.01); H01L 2224/05681 (2013.01); H01L 2224/05686 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/1191 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13005 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/94 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.


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