The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Jan. 12, 2012
Applicants:

Rezaur Rahman Khan, Rancho Santa Margarita, CA (US);

Sam Ziqun Zhao, Irvine, CA (US);

Pieter Vorenkamp, Laguna Niguel, CA (US);

Kevin Kunzhong HU, Irvine, CA (US);

Sampath K. V. Karikalan, Irvine, CA (US);

Xiangdong Chen, Irvine, CA (US);

Inventors:

Rezaur Rahman Khan, Rancho Santa Margarita, CA (US);

Sam Ziqun Zhao, Irvine, CA (US);

Pieter Vorenkamp, Laguna Niguel, CA (US);

Kevin Kunzhong Hu, Irvine, CA (US);

Sampath K. V. Karikalan, Irvine, CA (US);

Xiangdong Chen, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/13 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/13 (2013.01); H01L 23/49833 (2013.01); H01L 25/0657 (2013.01); H01L 23/49827 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.


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