The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2016
Filed:
Aug. 25, 2015
United Microelectronics Corp., Hsin-Chu, TW;
Chao-Hung Lin, Changhua County, TW;
Chih-Kai Hsu, Tainan, TW;
Li-Wei Feng, Kaohsiung, TW;
Shih-Hung Tsai, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Jyh-Shyang Jenq, Pingtung County, TW;
Ching-Wen Hung, Tainan, TW;
Jia-Rong Wu, Kaohsiung, TW;
Yi-Hui Lee, Taipei, TW;
Ying-Cheng Liu, Tainan, TW;
Yi-Kuan Wu, Kaohsiung, TW;
Chih-Sen Huang, Tainan, TW;
Yi-Wei Chen, Taichung, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.