logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9508716 B1

PDFFull Text
Date of Patent:
Nov. 29, 2016

Filed:

Apr. 11, 2013

Methods of manufacturing a semiconductor device

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Tung Lin, Jhudong Township, TW;

Teng-Chun Tsai, Hsin-Chu, TW;

Li-Ting Wang, Tainan, TW;

Chi-Yuan Chen, Hsin-Chu, TW;

Kuo-Yin Lin, Jhubei, TW;

Wan-Chun Pan, Hsin-Chu, TW;

Ming-Liang Yen, New Taipei, TW;

Ching-Wei Tsai, Taoyuan, TW;

Kuo-Cheng Ching, Zhubei, TW;

Huicheng Chang, Tainan, TW;

Chih-Hao Wang, Hsin-Chu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Mary Wilczewski

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 21/8258 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/28512 (2013.01); H01L 21/28518 (2013.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/8258 (2013.01); H01L 21/823418 (2013.01); H01L 21/823814 (2013.01); H01L 23/485 (2013.01); H01L 27/0629 (2013.01); H01L 27/088 (2013.01); H01L 27/0928 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece including an n-type field effect transistor (N-FET) region, a p-type FET (P-FET) region, and an insulating material disposed over the N-FET region and the P-FET region. The method includes patterning the insulating material to expose a portion of the N-FET region and a portion of the P-FET region, and forming an oxide layer over the exposed portion of the N-FET region and the exposed portion of the P-FET region. The oxide layer over the P-FET region is altered, and a metal layer is formed over a portion of the N-FET region and the P-FET region. The workpiece is annealed to form a metal-insulator-semiconductor (MIS) tunnel diode over the N-FET region and a silicide or germinide material over the P-FET region.

Find Patent Forward Citations

Loading…