The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jun. 05, 2015
Applicant:

Utac Headquarters Pte. Ltd., Singapore, SG;

Inventors:

Nathapong Suthiwongsunthorn, Singapore, SG;

Antonio Jr. Bambalan Dimaano, Singapore, SG;

Rui Huang, Singapore, SG;

Hua Hong Tan, Singapore, SG;

Kriangsak Sae Le, Bangkok, TH;

Beng Yeung Ho, Singapore, SG;

Nelson Agbisit De Vera, Singapore, SG;

Roel Adeva Robles, Singapore, SG;

Wedanni Linsangan Micla, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/3105 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 21/3105 (2013.01); H01L 21/561 (2013.01); H01L 21/566 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/544 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68336 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/1134 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/94 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/1815 (2013.01);
Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.


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