The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Jul. 06, 2015
Applicants:
Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Inventors:
Shay Reboh, Sassenage, FR;
Laurent Grenouillet, Rives, FR;
Cyrille Le Royer, Tullins Fures, FR;
Sylvain Maitrejean, Grenoble, FR;
Yves Morand, Grenoble, FR;
Assignees:
Commissariat a l'energie atomique et aux energies alternatives, Paris, FR;
STMICROELECTRONICS (CROLLES 2) SAS, Crolles, FR;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7847 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02667 (2013.01); H01L 21/26506 (2013.01); H01L 29/66772 (2013.01); H01L 29/7849 (2013.01); H01L 29/66477 (2013.01);
Abstract
Method to strain a channel zone of a transistor of the semiconductor on insulator type transistor that makes use of an SMT stress memorization technique in which regions located under the insulation layer of the substrate (FIG.) are amorphized, before the transistor gate is made.