The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
Aug. 25, 2015
Sandisk Technologies Inc., Plano, TX (US);
Zhenyu Lu, Milpitas, CA (US);
Henry Chien, San Jose, CA (US);
Johann Alsmeier, San Jose, CA (US);
Koji Miyata, Yokkaichi, JP;
Tong Zhang, Palo Alto, CA (US);
Man Mui, Fremont, CA (US);
James Kai, Santa Clara, CA (US);
Wenguang Shi, Milpitas, CA (US);
Wei Zhao, Milpitas, CA (US);
Xiaolong Hu, Yokkaichi, JP;
Jiyin Xu, Yokkaichi, JP;
Gerrit Jan Hemink, Milpitas, CA (US);
Christopher Petti, Mountain View, CA (US);
SANDISK TECHNOLOGIES LLC, Plano, TX (US);
Abstract
A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.