The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Oct. 31, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

I-Chih Chen, Tainan, TW;

Fu-Tsun Tsai, Tainan, TW;

Yung-Fa Lee, Tainan, TW;

Ko-Min Lin, Tainan, TW;

Chih-Mu Huang, Tainan, TW;

Ying-Lang Wang, Tai-Chung County, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 21/324 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/285 (2006.01); H01L 29/165 (2006.01); H01L 21/265 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66636 (2013.01); H01L 21/28518 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/41775 (2013.01); H01L 29/41783 (2013.01); H01L 29/665 (2013.01); H01L 29/66628 (2013.01); H01L 29/7848 (2013.01); H01L 21/26506 (2013.01); H01L 21/76814 (2013.01);
Abstract

A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.


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