The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2016
Filed:
Jul. 18, 2015
Applicant:
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Inventors:
Yoshiki Yamamoto, Kanagawa, JP;
Hideki Makiyama, Kanagawa, JP;
Toshiaki Iwamatsu, Kanagawa, JP;
Takaaki Tsunomura, Kanagawa, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/266 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/266 (2013.01); H01L 29/41783 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66628 (2013.01); H01L 29/66666 (2013.01); H01L 29/66772 (2013.01); H01L 29/78621 (2013.01); H01L 29/665 (2013.01);
Abstract
A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.