The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
Jun. 04, 2014
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Cheng-Tung Lin, Hsinchu County, TW;
Teng-Chun Tsai, Hsinchu, TW;
Li-Ting Wang, Hsinchu, TW;
De-Fang Chen, Hsinchu, TW;
Chih-Tang Peng, Hsinchu County, TW;
Hung-Ta Lin, Hsinchu, TW;
Chien-Hsun Wang, Hsinchu, TW;
Huang-Yi Huang, Hsin-chu, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
Structures and methods are provided for forming bottom source/drain contact regions for nanowire devices. A nanowire is formed on a substrate. The nanowire extends substantially vertically relative to the substrate and is disposed between a top source/drain region and a bottom source/drain region. A first dielectric material is formed on the bottom source/drain region. A second dielectric material is formed on the first dielectric material. A first etching process is performed to remove part of the first dielectric material and part of the second dielectric material to expose part of the bottom source/drain region. A second etching process is performed to remove part of the first dielectric material under the second dielectric material to further expose the bottom source/drain region. A first metal-containing material is formed on the exposed bottom source/drain region. Annealing is performed to form a bottom contact region.