The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Sep. 11, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-wen Cheng, Zhubei, TW;

Jung-Huei Peng, Jhubei, TW;

Shang-Ying Tsai, Pingzhen, TW;

Hung-Chia Tsai, Taichung, TW;

Yi-Chuan Teng, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); B81B 7/02 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81B 7/02 (2013.01); B81C 1/00301 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0264 (2013.01); B81B 2207/07 (2013.01); B81B 2207/094 (2013.01); B81B 2207/095 (2013.01); B81C 2203/0154 (2013.01); B81C 2203/0771 (2013.01); H01L 21/568 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.


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