The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2016
Filed:
Apr. 25, 2013
Prashant Majhi, Austin, TX (US);
Mantu K. Hudait, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Titash Rakshit, Hillsboro, OR (US);
Willman Tsai, Saratoga, CA (US);
Prashant Majhi, Austin, TX (US);
Mantu K. Hudait, Portland, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Gilbert Dewey, Hillsboro, OR (US);
Titash Rakshit, Hillsboro, OR (US);
Willman Tsai, Saratoga, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.