The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2016
Filed:
Apr. 15, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Jyuh-Fuh Lin, Miaoli County, TW;
Pei-Yi Liu, Changhua County, TW;
Cheng-Hung Chen, Hsinchu County, TW;
Wen-Chuan Wang, Hsinchu, TW;
Shy-Jay Lin, Hsinchu County, TW;
Burn Jeng Lin, HsinChu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.