The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2016
Filed:
Apr. 14, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Jyuh-Fuh Lin, Miaoli County, TW;
Pei-Yi Liu, Changhua County, TW;
Cheng-Hung Chen, Hsinchu County, TW;
Wen-Chuan Wang, Hsinchu, TW;
Shy-Jay Lin, Hsinchu County, TW;
Burn Jeng Lin, HsinChu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
The present disclosure provides a method that includes receiving an IC design layout having main features and generating a plurality of space block layers to the IC design layout. The method also includes calculating main pattern density PDand dummy pattern density PDof the IC design layout and calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space block layers according to the main pattern density and the dummy pattern density. The method further includes choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR and generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio. Additionally, the method includes forming a tape-out data of the modified IC design layout for IC fabrication.