The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 30, 2016

Filed:

Dec. 13, 2012
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Lai Wei Chih, Hsin-Chu, TW;

Monsen Liu, Zhudong Township, TW;

En-Hsiang Yeh, Hsin-Chu, TW;

Chuei-Tang Wang, Taichung, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 1/38 (2006.01); H01L 23/00 (2006.01); H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01Q 1/22 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 23/66 (2013.01); H01L 24/19 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01Q 1/2283 (2013.01);
Abstract

An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.


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