The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2016
Filed:
Dec. 18, 2014
Mie Fujitsu Semiconductor Limited, Kuwana, JP;
Scott E. Thompson, Gainesville, FL (US);
Thomas Hoffmann, Los Gatos, CA (US);
Lance Scudder, Sunnyvale, CA (US);
Urupattur C. Sridharan, San Jose, CA (US);
Dalong Zhao, San Jose, CA (US);
Pushkar Ranade, Los Gatos, CA (US);
Michael Duane, Santa Clara, CA (US);
Paul Gregory, Palo Alto, CA (US);
Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;
Abstract
Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.