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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9385201 B1

PDFFull Text
Date of Patent:
Jul. 05, 2016

Filed:

Jun. 06, 2014

Buried source-drain contact for integrated circuit transistor devices and method of making same

Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

Globalfoundries Inc, Grand Cayman, KY;

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Qing Liu, Watervliet, NY (US);

Ruilong Xie, Schenectady, NY (US);

Chun-Chen Yeh, Clifton Park, NY (US);

Xiuyu Cai, Niskayuna, NY (US);

William J. Taylor, Clifton Park, NY (US);

Assignees:

STMICROELECTRONICS, INC., Coppell, TX (US);

GLOBALFOUNDRIES INC, Grand Cayman, KY;

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorney:

Gardere Wynne Sewell LLP

Primary Examiner:

Benjamin Sandvik

Assistant Examiner:

Herve Assouman

Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Find Patent Forward Citations

Liu, Qing. (2016). Buried source-drain contact for integrated circuit transistor devices and method of making same (U.S. Patent No. 9385201). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9385201

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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