The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2016
Filed:
Mar. 17, 2015
Applicants:
Hun Teak Lee, Seongnam-si, KR;
Youngchul Kim, Youngin-si, KR;
Hyunll Bae, Seoul, KR;
Heesoo Lee, Anyang-si, KR;
Heejo Chi, Yeoju-gun, KR;
Inventors:
Hun Teak Lee, Seongnam-si, KR;
YoungChul Kim, Youngin-si, KR;
Hyunll Bae, Seoul, KR;
HeeSoo Lee, Anyang-si, KR;
HeeJo Chi, Yeoju-gun, KR;
Assignee:
STATS ChipPAC Pte. Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 21/563 (2013.01); H01L 24/81 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81395 (2013.01); H01L 2224/81447 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/0541 (2013.01); H01L 2924/14 (2013.01);
Abstract
An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.