The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2016
Filed:
Jan. 24, 2014
Intel Corporation, Santa Clara, CA (US);
Christopher J. Jezewski, Hillsboro, OR (US);
Jasmeet S. Chawla, Hillsboro, OR (US);
Kanwal Jit Singh, Hillsboro, OR (US);
Alan M. Myers, Beaverton, OR (US);
Elliot N. Tan, Portland, OR (US);
Richard E. Schenker, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.