The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Nov. 07, 2013
Applicant:

Novellus Systems, Inc., Fremont, CA (US);

Inventors:

Shankar Swaminathan, Hillsboro, OR (US);

Bart van Schravendijk, Cupertino, CA (US);

Adrien LaVoie, Newberg, OR (US);

Sesha Varadarajan, Lake Oswego, OR (US);

Jason Daejin Park, San Jose, CA (US);

Michal Danek, Cupertino, CA (US);

Naohiro Shoda, Los Gatos, CA (US);

Assignee:

Novellus Systems, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/67 (2006.01); H01L 21/02 (2006.01); C23C 16/04 (2006.01); C23C 16/455 (2006.01); C23C 16/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); C23C 16/045 (2013.01); C23C 16/45523 (2013.01); C23C 16/56 (2013.01); H01L 21/0228 (2013.01); H01L 21/02126 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/67017 (2013.01);
Abstract

A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.


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