The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Dec. 02, 2012
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Jiro Yugami, Kanagawa, JP;
Toshiaki Iwamatsu, Kanagawa, JP;
Katsuyuki Horita, Kanagawa, JP;
Hideki Makiyama, Kanagawa, JP;
Yasuo Inoue, Kanagawa, JP;
Yoshiki Yamamoto, Kanagawa, JP;
Renesas Electronics Corporation, Tokyo, JP;
Abstract
A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.