The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Dec. 25, 2013
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Hung Chen, Tainan, TW;

Ming-Tse Lin, Hsinchu, TW;

Yung-Chang Lin, Taichung, TW;

Chien-Li Kuo, Hsinchu, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); H01L 21/76846 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/525 (2013.01); H01L 23/53238 (2013.01); H01L 2224/023 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02315 (2013.01); H01L 2224/02373 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.


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