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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9343302 B1

PDFFull Text
Date of Patent:
May. 17, 2016

Filed:

Dec. 16, 2014

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Been-Yih Jin, Taipei, TW;

Brian S. Doyle, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Winkle, PLLC

Primary Examiner:

Laura Menz

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); B82Y 10/00 (2011.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/10 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/316 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02603 (2013.01); B82Y 10/00 (2013.01); H01L 21/0245 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/02381 (2013.01); H01L 21/02507 (2013.01); H01L 21/02532 (2013.01); H01L 21/30604 (2013.01); H01L 21/76283 (2013.01); H01L 29/068 (2013.01); H01L 29/0665 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/42324 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); H01L 21/31658 (2013.01); H01L 21/823807 (2013.01); H01L 29/66818 (2013.01);
Abstract

A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1−xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1−yGey and a covering region comprising SiO2 and enclosing the center region.

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