The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Aug. 23, 2011
Applicants:
Yi-chao Wang, Hsin-Chu, TW;
Yu-chang Lin, Linkou Shiang, TW;
Li-ting Wang, Tainin, TW;
Tai-chun Huang, Hsin-Chu, TW;
Pei-ren Jeng, Chu-Bei, TW;
Tze-liang Lee, Hsin-Chu, TW;
Inventors:
Yi-Chao Wang, Hsin-Chu, TW;
Yu-Chang Lin, Linkou Shiang, TW;
Li-Ting Wang, Tainin, TW;
Tai-Chun Huang, Hsin-Chu, TW;
Pei-Ren Jeng, Chu-Bei, TW;
Tze-Liang Lee, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/324 (2006.01); H01L 21/268 (2006.01); H01L 21/20 (2006.01); H01L 21/36 (2006.01); H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
H01L 21/324 (2013.01); H01L 21/268 (2013.01);
Abstract
A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.