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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9337049 B1

PDFFull Text
Date of Patent:
May. 10, 2016

Filed:

Apr. 23, 2015

Manufacturing method of wafer level chip scale package structure

Applicants:

Niko Semiconductor Co., Ltd., New Taipei, TW;

Super Group Semiconductor Co., Ltd., New Taipei, TW;

Inventors:

Chih Cheng Hsieh, Taoyuan County, TW;

Hsiu Wen Hsu, Hsinchu County, TW;

Assignees:

NIKO SEMICONDUCTOR CO., LTD., New Taipei, TW;

SUPER GROUP SEMICONDUCTOR CO., LTD., New Taipei, TW;

Attorney:

Li & Cai Intellectual Property (USA) Office

Primary Examiner:

Jaehwan Oh

Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/78 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/4842 (2013.01); H01L 21/76852 (2013.01); H01L 21/76895 (2013.01); H01L 21/78 (2013.01); H01L 29/7827 (2013.01);
Abstract

A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.

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