The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
May. 14, 2012
Izumi Fusegawa, Nishishirakawa, JP;
Ryoji Hoshi, Nishishirakawa, JP;
Susumu Sonokawa, Nishishirakawa, JP;
Hisayuki Saito, Nishishirakawa, JP;
Izumi Fusegawa, Nishishirakawa, JP;
Ryoji Hoshi, Nishishirakawa, JP;
Susumu Sonokawa, Nishishirakawa, JP;
Hisayuki Saito, Nishishirakawa, JP;
SHIN-ETSU HANDOTAI CO., LTD., Tokyo, JP;
Abstract
Methods for producing a silicon wafer from a defect-free silicon single crystal grown by a Czochralski (CZ) method are provided. The methods comprise: preparing a silicon wafer obtained by slicing the defect-free silicon single crystal and subjected to mirror-polishing; then performing a heat treatment step of subjecting the mirror-polished silicon wafer to heat treatment at a temperature of 500° C. or higher but 600° C. or lower for 4 hours or more but 6 hours or less; and performing a repolishing step of repolishing the silicon wafer after the heat treatment step such that a polishing amount becomes 1.5 μm or more. Therefore, it is an object to provide a method by which a silicon wafer can be produced at a high yield, the silicon wafer in which Light Point Defects (LPDs) are reduced to a minimum, the silicon wafer with a low failure-incidence rate in an inspection step and a shipment stage.