The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jul. 27, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Shih-Wen Liu, Taoyuan, TW;

Mei-Yun Wang, Chu-Pei, TW;

Hsien-Cheng Wang, Hsinchu, TW;

Fu-Kai Yang, Hsinchu, TW;

Hsiao-Chiu Hsu, Hsinchu, TW;

Hsin-Ying Lin, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/823475 (2013.01); H01L 27/088 (2013.01); H01L 29/0653 (2013.01); H01L 29/401 (2013.01); H01L 29/4175 (2013.01); H01L 29/45 (2013.01); H01L 29/66484 (2013.01); H01L 29/66795 (2013.01);
Abstract

A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.


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