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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9324709 B1

PDFFull Text
Expired
Date of Patent:
Apr. 26, 2016

Filed:

Aug. 19, 2013

Self-aligned gate contact structure

Applicant:

Global Foundries U.s. 2 Llc, Hopewell Junction, NY (US);

Inventors:

Veeraraghavan S. Basker, Schenectady, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Ali Khakifirooz, Mountain View, CA (US);

Viraj Y. Sardesai, Poughkeepsie, NY (US);

Raghavasimhan Sreenivasan, Schenectady, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY (US);

Attorneys:

Yuanmin Cai

Hoffman Warnick LLC

Primary Examiner:

Tucker J Wright

Assistant Examiner:

Mark Hatzilambrou

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/823456 (2013.01); H01L 21/823475 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01);
Abstract

Embodiments of present invention provide a method of forming a semiconductor device. The method includes depositing a layer of metal over one or more channel regions of respective one or more transistors in a substrate, the layer of metal having a first region and a second region; lowering height of the first region of the layer of metal; forming an insulating layer over the first region of lowered height, the insulating layer being formed to have a top surface coplanar with the second region of the layer of metal; and forming at least one contact to a source/drain region of the one or more transistors. Structure of the semiconductor device formed thereby is also provided.

Find Patent Forward Citations

Basker, Veeraraghavan. (2016). Self-aligned gate contact structure (U.S. Patent No. 9324709). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9324709

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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