The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Jun. 19, 2012
Applicants:

Byung Tai DO, Singapore, SG;

Arnel Senosa Trasporto, Singapore, SG;

Linda Pei EE Chua, Singapore, SG;

Emmanuel Espiritu, Singapore, SG;

Inventors:

Byung Tai Do, Singapore, SG;

Arnel Senosa Trasporto, Singapore, SG;

Linda Pei Ee Chua, Singapore, SG;

Emmanuel Espiritu, Singapore, SG;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 21/568 (2013.01); H01L 21/4832 (2013.01); H01L 23/49548 (2013.01); H01L 23/49575 (2013.01); H01L 23/49582 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01); Y10T 29/4921 (2015.01);
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.


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