The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Sep. 15, 2010
Applicants:

Leo A. Merilo, Singapore, SG;

Emmanuel A. Espiritu, Singapore, SG;

Dario S. Filoteo, Jr., Singapore, SG;

Rachel L. Abinan, Singapore, SG;

Inventors:

Leo A. Merilo, Singapore, SG;

Emmanuel A. Espiritu, Singapore, SG;

Dario S. Filoteo, Jr., Singapore, SG;

Rachel L. Abinan, Singapore, SG;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 25/16 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/162 (2013.01); H01L 24/49 (2013.01); H01L 23/3128 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.


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