The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2016
Filed:
Jul. 09, 2012
Anatoly Romanovsky, Palo Alto, CA (US);
Ivan Maleev, Pleasanton, CA (US);
Daniel Kavaldjiev, San Jose, CA (US);
Yury Yuditsky, Mountain View, CA (US);
Dirk Woll, San Jose, CA (US);
Stephen Biellak, Sunnyvale, CA (US);
Mehdi Vaez-iravani, Los Gatos, CA (US);
Guoheng Zhao, Palo Alto, CA (US);
Anatoly Romanovsky, Palo Alto, CA (US);
Ivan Maleev, Pleasanton, CA (US);
Daniel Kavaldjiev, San Jose, CA (US);
Yury Yuditsky, Mountain View, CA (US);
Dirk Woll, San Jose, CA (US);
Stephen Biellak, Sunnyvale, CA (US);
Mehdi Vaez-Iravani, Los Gatos, CA (US);
Guoheng Zhao, Palo Alto, CA (US);
KLA-Tencor Corp., Milpitas, CA (US);
Abstract
Systems configured to inspect a wafer are provided. One system includes an illumination subsystem configured to simultaneously form multiple illumination areas on the wafer with substantially no illumination flux between each of the areas. The system also includes a scanning subsystem configured to scan the multiple illumination areas across the wafer. In addition, the system includes a collection subsystem configured to simultaneously and separately image light scattered from each of the areas onto two or more sensors. Characteristics of the two or more sensors are selected such that the scattered light is not imaged into gaps between the two or more sensors. The two or more sensors generate output responsive to the scattered light. The system further includes a computer subsystem configured to detect defects on the wafer using the output of the two or more sensors.