The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2016

Filed:

Mar. 18, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

WonJun Ko, Kyungki-Do, KR;

SeungYong Chai, Gyeonggi-do, KR;

OhHan Kim, Kyonggi-do, KR;

GwangTae Kim, Seoul, KR;

Kenny Lee, Seoul, KR;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01K 15/00 (2006.01); G01N 25/72 (2006.01); G01N 3/20 (2006.01); G01B 11/30 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01B 11/306 (2013.01); H01L 22/12 (2013.01);
Abstract

A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.


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