The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Sep. 26, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Anthony I-Chih Chou, Beacon, NY (US);

Arvind Kumar, Beacon, NY (US);

Shreesh Narasimha, Beacon, NY (US);

Claude Ortolland, Peekskill, NY (US);

Kai Zhao, Hopewell Junction, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/51 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/518 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 27/0924 (2013.01); H01L 29/511 (2013.01);
Abstract

Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.


Find Patent Forward Citations

Chou, Anthony I-Chih. (2016). Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-k metal gate field effect transistors (U.S. Patent No. 9269786). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9269786

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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