The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Nov. 27, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Wen-Tai Lu, Hsinchu, TW;

Hou-Yu Chen, Zhubei, TW;

Yu-Chang Lin, Hsinchu, TW;

Chun-Feng Nieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7847 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7843 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66871 (2013.01); H01L 2924/13067 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.


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