The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2016

Filed:

Apr. 01, 2012
Applicants:

Chi-ming Tsai, New Taipei, TW;

Liang-guang Chen, Hsinchu, TW;

Han-hsin Kuo, Tainan, TW;

Fu-ming Huang, Changhua County, TW;

Hao-jen Liao, Taichung, TW;

Ming-chung Liang, Hsin-Chu, TW;

Inventors:

Chi-Ming Tsai, New Taipei, TW;

Liang-Guang Chen, Hsinchu, TW;

Han-Hsin Kuo, Tainan, TW;

Fu-Ming Huang, Changhua County, TW;

Hao-Jen Liao, Taichung, TW;

Ming-Chung Liang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 22/30 (2013.01); H01L 21/7684 (2013.01); H01L 23/522 (2013.01); H01L 2924/0002 (2013.01);
Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.


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