The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Nov. 03, 2014
Applicant:

Chipbond Technology Corporation, Hsinchu, TW;

Inventors:

Cheng-Hung Shih, Changhua County, TW;

Kuo-Hua Yang, Hsinchu, TW;

Hsiang-Pin Hou, New Taipei, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/311 (2013.01);
Abstract

A method of photoresist strip includes providing a semiconductor substrate and performing an immerse step and a strip step, wherein the semiconductor substrate comprises a base, a bonding pad, a protective layer, an under bump metallurgy layer, a patterned photoresist layer and a bump. The patterned photoresist layer covers the under bump metallurgy layer and a lateral surface of the bump, wherein a first connection interface is formed between the patterned photoresist layer and the lateral surface of the bump, and a second connection interface is formed between the patterned photoresist layer and the under bump metallurgy layer. In the immerse step, the patterned photoresist layer contacts with a chemical solution which degrades the bond strength of the first connection interface. Therefore, in the strip step, the semiconductor substrate is scoured by a flow with appropriate force of impact, which strips the patterned photoresist layer from the base.


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