The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Jan. 18, 2013
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wen-Jiun Liu, Zhunan Township, Miaoli County, TW;

Chien-An Chen, Zhubei, TW;

Ya-Lien Lee, Baoshan Township, Hsinchu County, TW;

Hung-Wen Su, Jhubei, TW;

Minghsing Tsai, Chu-Pei, TW;

Syun-Ming Jang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/768 (2013.01); H01L 21/76885 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 21/76852 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.


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