The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Dec. 19, 2011
Applicants:

Jacob Jensen, Beaverton, OR (US);

Tahir Ghani, Portland, OR (US);

Mark Y. Liu, West Linn, OR (US);

Harold Kennel, Portland, OR (US);

Robert James, Portland, OR (US);

Inventors:

Jacob Jensen, Beaverton, OR (US);

Tahir Ghani, Portland, OR (US);

Mark Y. Liu, West Linn, OR (US);

Harold Kennel, Portland, OR (US);

Robert James, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/268 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 21/268 (2013.01); H01L 21/76805 (2013.01); H01L 29/66628 (2013.01); H01L 21/76883 (2013.01);
Abstract

Laser anneal to melt regions of a microelectronic device buried under overlying materials, such as an interlayer dielectric (ILD). Melting temperature differentiation is employed to selectively melt a buried region. In embodiments a buried region is at least one of a gate electrode and a source/drain region. Laser anneal may be performed after contact formation with contact metal coupling energy into the buried layer for the anneal.


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