The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Aug. 04, 2011
Applicants:

Isik C. Kizilyalli, San Francisco, CA (US);

Hui Nie, Cupertino, CA (US);

Andrew P. Edwards, San Jose, CA (US);

Linda Romano, Sunnyvale, CA (US);

David P. Bour, Cupertino, CA (US);

Richard J. Brown, Los Gatos, CA (US);

Thomas R. Prunty, Santa Clara, CA (US);

Inventors:

Isik C. Kizilyalli, San Francisco, CA (US);

Hui Nie, Cupertino, CA (US);

Andrew P. Edwards, San Jose, CA (US);

Linda Romano, Sunnyvale, CA (US);

David P. Bour, Cupertino, CA (US);

Richard J. Brown, Los Gatos, CA (US);

Thomas R. Prunty, Santa Clara, CA (US);

Assignee:

Avogy, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 29/808 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8083 (2013.01); H01L 29/1066 (2013.01); H01L 29/66924 (2013.01); H01L 29/2003 (2013.01); H01L 29/66446 (2013.01);
Abstract

A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.


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