The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Nov. 15, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hsien-Chieh Tsai, Taichung, TW;
Tz-Wei Lin, Taichung, TW;
Sheng-Jen Yang, Taichung, TW;
Hung-Yin Lin, Taichung, TW;
Cherng-Chang Tsuei, Hsinchu, TW;
Chen-Hsiang Lu, Hsin-Chu, TW;
TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.