The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Aug. 28, 2013
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Joachim Patzer, Langebrueck, DE;

Ardechir Pakfar, Dresden, DE;

Dominic Thurmer, Dresden, DE;

Chih-Chun Wang, Dresden, DE;

Remi Riviere, Dresden, DE;

Robert Melzer, Radebeul, DE;

Bastian Haussdoerfer, Dresden, DE;

Martin Weisheit, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 21/823828 (2013.01); H01L 21/823878 (2013.01); H01L 27/0629 (2013.01); H01L 21/31058 (2013.01); H01L 21/31144 (2013.01);
Abstract

A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.


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