The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Jan. 06, 2012
Applicants:

Jaspreet S. Gandhi, Boise, ID (US);

Brandon P. Wirz, Kuna, ID (US);

Yangyang Sun, Boise, ID (US);

Josh D. Woodland, Kuna, ID (US);

Inventors:

Jaspreet S. Gandhi, Boise, ID (US);

Brandon P. Wirz, Kuna, ID (US);

Yangyang Sun, Boise, ID (US);

Josh D. Woodland, Kuna, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/29 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/563 (2013.01); H01L 23/293 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0657 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/11822 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/1369 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13562 (2013.01); H01L 2224/14131 (2013.01); H01L 2224/16058 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81011 (2013.01); H01L 2224/8123 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/81862 (2013.01); H01L 2224/81905 (2013.01); H01L 2224/83104 (2013.01); H01L 2924/00014 (2013.01);
Abstract

An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising opposing ends. A conductive bond pad is adjacent one of the ends on one side of the one substrate. A conductive solder mass is adjacent the other end projecting elevationally on the other side of the one substrate. Individual of the solder masses are bonded to a respective bond pad on an immediately adjacent substrate of the stack. Epoxy flux surrounds the individual solder masses. An epoxy material different in composition from the epoxy flux surrounds the epoxy flux on the individual solder masses. Methods of forming integrated circuit constructions are also disclosed.


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