The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2015
Filed:
Sep. 28, 2012
Sansaptak Dasgupta, Santa Clara, CA (US);
Han Wui Then, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Niti Goel, Austin, TX (US);
Sanaz Kabehie, Portland, OR (US);
Seung Hoon Sung, Beaverton, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Sansaptak Dasgupta, Santa Clara, CA (US);
Han Wui Then, Portland, OR (US);
Marko Radosavljevic, Beaverton, OR (US);
Niloy Mukherjee, Beaverton, OR (US);
Niti Goel, Austin, TX (US);
Sanaz Kabehie, Portland, OR (US);
Seung Hoon Sung, Beaverton, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Robert S. Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.