The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Jan. 17, 2012
Janusz Rajski, West Linn, OR (US);
Mark a Kassab, Wilsonville, OR (US);
Grzegorz Mrugalski, Swarzedz, PL;
Nilanjan Mukherjee, Wilsonville, OR (US);
Jakub Janicki, Poznan, PL;
Jerzy Tyszer, Poznan, PL;
Avijit Dutta, Tigard, OR (US);
Janusz Rajski, West Linn, OR (US);
Mark A Kassab, Wilsonville, OR (US);
Grzegorz Mrugalski, Swarzedz, PL;
Nilanjan Mukherjee, Wilsonville, OR (US);
Jakub Janicki, Poznan, PL;
Jerzy Tyszer, Poznan, PL;
Avijit Dutta, Tigard, OR (US);
Mentor Graphics Corporation, Wilsonville, OR (US);
Abstract
Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling for testing a plurality of cores in a system on circuit. Test data are encoded to derive compressed test patterns that require small numbers of core input channels. Core input/output channel requirement information for each of the compressed test patterns is determined accordingly. The compressed patterns are grouped into test pattern classes. The formation of the test pattern classes is followed by allocation circuit input and output channels and test application time slots that may comprise merging complementary test pattern classes into clusters that can work with a particular test access mechanism. The test access mechanism may be designed independent of the test data.