The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2015
Filed:
Feb. 03, 2014
Applicant:
Maxim Integrated Products, Inc., San Jose, CA (US);
Inventors:
Yong L. Xu, Plano, TX (US);
Viren Khandekar, Flower Mound, TX (US);
Yi-Sheng A. Sun, San Jose, CA (US);
Arkadii V. Samoilov, Saratoga, CA (US);
Assignee:
Maxim Integrated Products, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 24/94 (2013.01);
Abstract
Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.