The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2015

Filed:

Feb. 27, 2014
Applicant:

Pakal Technologies, Llc, San Francisco, CA (US);

Inventors:

Richard A. Blanchard, Los Altos, CA (US);

Hidenori Akiyama, Miyagi, JP;

Woytek Tworzydio, Austin, TX (US);

Vladimir Rodov, Seattle, WA (US);

Assignee:

Pakal Technologies LLC, San Francisco, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/739 (2006.01); H03K 17/30 (2006.01); H01L 29/745 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1095 (2013.01); H01L 29/7395 (2013.01); H01L 29/7455 (2013.01);
Abstract

An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.


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